Field of the Invention
The present invention relates to a voltage supply level detecting circuit, and more particularly, to a voltage supply level detecting circuit for detecting whether the voltage applied to a semiconductor memory device is high or low.
Description of the Prior Art
In some semiconductor memory devices, for example, an erasable programmable read only memory device (EPROM), two voltages are supplied to the circuit, i.e., a fixed voltage supply V.sub.CC (5 V) and a variable voltage supply V.sub.PP set to a high voltage level (21 V) when programming and at a low voltage level (5 V) when reading. In such a device, a detecting circuit detects whether the variable voltage supply is at the high or low voltage level. The output of the detecting circuit sets the operation of the memory device to the programming or reading mode.
There is a known a prior art V.sub.PP level detecting circuit which comprises a first depletion type N-channel transistor, a first enhancement type N-channel transistor, a second depletion type N-channel transistor, a second enhancement type N-channel transistor, a third depletion type N-channel transistor, and a third enhancement type N-channel transistor. The first depletion type transistor and the first enhancement type transistor are connected in series between the fixed voltage supply V.sub.CC and ground. The gate of the firs depletion type transistor is connected to its source, and the gate of the first enhancement type transistor is connected to the variable voltage supply V.sub.PP. The second depletion type transistor and the second enhancement type transistor are connected in series between the fixed voltage supply and ground. The gate of the second depletion type transistor is connected to its source, and the gate of the second enhancement type transistor is connected to the junction between the first depletion type transistor and the first enhancement type transistor. The third depletion type transistor and the third enhancement type transistor are connected in series between the fixed voltage supply V.sub.CC and ground. The gate of the third depletion type transistor is connected to its source, and the gate of the third enhancement type transistor is connected to the junction between the second depletion type transistor and the second enhancement type transistor.
In this prior art detecting circuit, the conductivity gm of the first enhancement transistor is designed to be small relative to the conductance gm of the first depletion transistor, so that when the variable voltage supply V.sub.PP is at the low level (5 V) the first enhancement transistor cannot be turned on fully and so that when the variable voltage supply V.sub.PP is at a high level (21 V), the first enhancement type transistor is fully turned on. Thus, the level of the junction between the first depletion type transistor and the first enhancement type transistor is at a relatively "high" level when the variable voltage supply V.sub.PP is a low level (5 V). Thus, the second enhancement type transistor is turned on, the third enhancement type transistor is turned off, and, the output level has a "high" level. On the other hand, when the variable voltage supply V.sub.PP is at a high level (21 V), the level of the junction between the first depletion type transistor and the first enhancement type transistor is at a relatively "low" level. Thus, the second enhancement type transistor is turned off, the third enhancement type transistor is turned on, and the output level has a "low" level.
In the above-mentioned prior art voltage supply level detecting circuit, the ratio of the dimensions of the first depletion type transistor and the first enhancement type transistor must be selected to be a predetermined value. Therefore, the construction of the circuit is difficult, and it is difficult to achieve stable circuit operation.
To counter these problems, there has been proposed another prior art voltage supply level detecting circuit, in which the second depletion type transistor in the above-mentioned circuit, connected between the fixed voltage supply and the second enhancement type transistor, is replaced by a group of enhancement type N-channel transistors, the gate of each is connected to its drain and the group is connected in series between the variable voltage supply and the second enhancement type transistor.
In this circuit, the sum of the threshold values of the group of the enhancement type transistors is selected to be more than the low voltage supply level (5 V). When the variable voltage supply is a low level (5 V), the first enhancement type transistor is turned on, but not fully, and the level of the junction between the first depletion type transistor and the first enhancement type transistor is relatively "high", so that the second enhancement type transistor is turned on. Since the voltage across the group of series-connected enhancement type transistors is lower than 5 V, at least one of these transistors is off. Thus, the level of the drain of the second enhancement type transistor has a low level. Thus, the third enhancement type transistor is returned off and the output has a "high" level.
On the other hand, when the variable voltage supply V.sub.PP is a high level (21 V), the first enhancement type transistor is fully turned on, the level of its drain has a "low" level, and the second enhancement type transistor is turned off. Thus, the level of the drain of the second enhancement type transistor has a "high" level, which level is lower than the high level of V.sub.PP by the sum of the threshold voltages of the group of the series-connected enhancement type transistors. Thus, the third enhancement type transistor is turned on, and the output has a "low" level.
In this prior art detecting circuit, at least one of the series-connected transistors is turned off when the variable voltage supply V.sub.PP is a low level, the second enhancement type transistor is not necessarily fully turned on. Accordingly, the dimension ratio of the first depletion type transistor and the first enhancement type transistor is not as critical as in the first mentioned prior art detecting circuit. However, in this second prior art detecting circuit, a large number of series-connected transistors are required in order to increase the sum of the threshold voltages of these transistors, and decrease the gate voltage of the third enhancement type transistor. Consequently, the number of components of this circuit is large.